Processing systems often utilize memory subsystems with multiple levels of caches. It often is advantageous to deactivate (that is, “power down”) such caches when not in use. To deactivate a cache, the cache is flushed and any valid lines are sent to system memory. However, power is consumed while searching the higher-level cache for valid cache lines to send to memory. Some conventional memory sub-systems utilize tracking hardware outside the cache to track a set of validity bits, sometimes referred to as “way valid” or “sector valid” bits, that indicate roughly occupied regions of the cache—that is, where valid cache lines are located within the cache, to help speed the search for the valid lines. The use of such validity bits can accelerate the flush if the valid lines are not spread widely over the cache. Nevertheless, the search for valid lines and the process of flushing a cache in preparation for deactivation of the cache utilizes a significant amount of power or a significant number of clock cycles.
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